The present invention disclosed herein relates to a frequency generator and a clock generator, and more particularly, to a spread spectrum clock generating circuit.
A Phase Locked Loop (PLL) generates an oscillation signal having a fixed frequency in response to a reference clock signal inputted from the external. The oscillation signal is provided as an operating clock of a system having the PLL.
Recently, as a system needs to operate at a higher speed and have the higher degree of integration so as to process digital data of a large capacity, a frequency of a clock signal that the system requires becomes higher. If a frequency of a clock signal becomes higher, Electro Magnetic Interference (EMI) may occur to cause system failure. That is, a high frequency signal (i.e., a clock signal) with high energy affects peripheral systems to cause malfunctions. In order to reduce EMI, a spread spectrum clock generating circuit is provided. The spread spectrum clock generating circuit adjusts an oscillation signal to distribute energy in frequencies of a broad band width.